Design and implementation of circuit optimization in VLSI: A review
Keywords:
Very Large-Scale Integration, Digital circuits, VLSI, VLSI designAbstract
Digital circuits streamline transistor functioning and enable switch-based device construction. There were significant drawbacks to the introduction of the vacuum tube into the electronics sector, such as the need for high power and a hundred anode tension. The development of the transistor required very little power in the field of microelectronics. It paved the way for future energy-efficient home appliances. Reduced functionality and more power per unit space have resulted from the integration of several functions onto a single chip and improved circuit performance, and these trends have been accompanied by an increase in the need for heat removal & cooling systems. Their primary problem in the VLSI setting is a lack of power. Today, optimization should focus on power, environment, and efficiency. The past was marked by extremely significant efficiency, expenditure, and production with a little weakening in power. The requirement for low power utilization and the high-speed processing has risen as a result of the incredible battery power development, a complicated practical technology like a computer system, electronic gadgets, mobile cellphones, implanted equipment, and digital portable devices. The high temperature activity of the powerful machine exacerbates the other defects in the silicone.
References
[1] Babu, A. (2014). Power Optimization Techniques at Circuit and Device Level in Digital CMOS VLSI - A Review. 3(11), 375-379.
[2] Circuits, V. (2018). A Literature Review on Design Strategies and Methodologies of Low Power A Literature Review on Design Strategies and Methodologies of Low Power VLSI Circuits. January 2014. https://doi.org/10.9790/4200-04241721
[3] Kaur, K. (2014). STRATEGIES & METHODOLOGIES FOR LOW POWER VLSI DESIGNS : A REVIEW. April 2011.
[4] Kumar, S. B. V., Rao, P. V, Sharath, H. A., Sachin, B. M., Ravi, U. S., & Monica, B. V. (2018). Review on VLSI design using optimization and self-adaptive particle swarm optimization. Journal of King Saud University - Computer and Information Sciences. https://doi.org/10.1016/j.jksuci.2018.01.001
[5] Kundan, N. N., & Engineering, C. (2020a). DESIGN AND IMPLEMENTATION OF CIRCUIT. 5(9), 33-39.
[6] Kundan, N. N., & Engineering, C. (2020b). Design and Implementation of Circuit Optimization in VLSI : A Review. 5(4), 476-482.
[7] Megha, M., Namratha, T. G., Divya, V., & E, P. K. (2020). Design Optimization in Digital System Design Design Optimization in Digital System Design Output Control Data path. May.
[8] Patil, S. (2015). Circuit Optimization and Design Automation Techniques for Low Power CMOS VLSI Design : A Review Circuit Optimization and Design Automation Techniques for Low Power CMOS VLSI Design : A Review. May.
[9] Poornima, G., Uttarkar, C., & Tomar, S. K. (2020). Timing And Power Optimization In Digital VLSI Circuits. July. https://doi.org/10.13140/RG.2.2.10953.98407
[10] Radfar, M., Shah, K., & Singh, J. (2012). Recent Subthreshold Design Techniques. 2012. https://doi.org/10.1155/2012/926753
[11] Singh, S., Saurav, S., Saini, R., Saini, A. K., Shekhar, C., & Vohra, A. (2014). Comprehensive Review and Comparative Analysis of Hardware Architectures for Sobel Edge Detector. 2014.https://doi.org/10.1155/2014/857912
[12] Sivakumar, M., & Omkumar, S. (2017). Implementation of Area & Power Optimized VLSI Circuits Using Logic Implementation of Area & Power Optimized VLSI Circuits Using Logic Techniques. January. https://doi.org/10.9790/4200-0704011523
[13] Sowmya, N., & Rout, S. S. (2021). A Review on VLSI Implementation in Biomedical Application A Review on VLSI Implementation in Biomedical Application (Issue January). Springer International Publishing. https://doi.org/10.1007/978-3-030-49339-4
[14] Thakur, N., & Kumar, D. (2021). Review Paper on Low Power VLSI Design Techniques Available Online at www.ijeecse.com Review Paper on Low Power VLSI Design Techniques. May, 13-18.
[15] Yadav, S. K. (2020). Optimization of Power Consumption in Cmos Vlsi Circuit Using Different Clusters. July.
