A Comprehensive Review on Recent Developments in Pattern Matching Techniques
Keywords:
Artificial Neural Networks, Application To Pattern Recognition, Field-Programmable Gate ArrayAbstract
Several different design methodologies have been used to build pattern matching procedures for network security. Global Positioning Systems (GPPs), application-specific integrated circuits, and configurable hardware designs such as field-programmable gate-arrays are often utilized in these techniques/methods. GPPs provide scalability and flexibility, but at a cost of lower performance and efficiency. However, the capacity to scale is not considered while designing Application-Specific Integrated Circuit (ASIC). However, Field-Programmable Gate Array (FPGA)-based hardware solutions provide a wide range of performance and scalability design options. Considering this, scalable hardware designs for pattern matching procedures are gaining in popularity. In addition, the implementation of pattern matching is hampered by the complexity of these systems' architectural layouts. Because of this, it is necessary to conduct a comprehensive investigation to identify and define current scalable hardware designs.
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